Phase change memory with doped silicon germanium alloy-containing electrodes and air gap-containing spacer

ABSTRACT

A PCM cell is provided that includes a phase change memory material that is sandwiched between top and bottom electrodes which are both composed of a doped silicon germanium alloy. A doped silicon germanium alloy has good electrical conductivity, while having a lower thermal conductivity than conventional conductive materials such as TiN or W that are typically used in PCM cells. The presence of the doped silicon germanium alloy mitigates heat loss in the PCM cell thus reducing reset current and, in some embodiments, thermal cross-talk between adjacent PCM cells. Further reduction of heat loss can be obtained by providing an airgap-containing dielectric spacer laterally adjacent to the PCM cell.

BACKGROUND

The present application relates to a semiconductor structure and amethod of forming the same. More particularly, the present applicationrelates to a semiconductor structure including a phase change memory(PCM) cell having a reduced reset current and reduced thermalcross-talk.

Phase change memory (PCM) has emerged as a viable technology to fill thememory application gap between volatile memory and flash memory. PCM isa type of non-volatile random access memory (NVRAM). A NVRAM retains itsinformation when the power is turned off. This is in contrast to dynamicrandom access memory (DRAM) and static random access memory (SRAM),which both maintain data only for as long as power is applied.

A typically PCM includes a material stack of, and from bottom to top, abottom electrode, a phase change memory material that exhibits a changein atomic order (from crystalline to amorphous, or vice versa), and atop electrode. The top and bottom electrodes are composed of aconductive material such as, for example, titanium nitride (TiN) ortungsten (W). Such conductive materials are also thermal conductors soheat loss occurs through the top and bottom electrodes of the PCM cell.

Heat loss in a PCM cell causes the following two issues, which areproblematic in PCM cells. First, due to heat loss higher current isrequired to reset a PCM cell and thus higher power consumption isneeded. Second, and for a highly scaled PCM cell array in which PCMcells are closely packed, heat from a PCM cell during the resetoperation may transfer to adjacent PCM cells, undesirably disturbing theadjacent PCM cells. There is thus a need for providing PCM cells inwhich heat loss is mitigated thus reducing reset current and thermalcross-talk between adjacent PCM cells.

SUMMARY

A PCM cell is provided that includes a phase change memory material thatis sandwiched between top and bottom electrodes which are both composedof a doped silicon germanium alloy. A doped silicon germanium alloy hasgood electrical conductivity, while having a lower thermal conductivitythan conventional conductive materials such as TiN or W that aretypically used in PCM cells. The presence of the doped silicon germaniumalloy mitigates heat loss in the PCM cell thus reducing reset currentand, in some embodiments, thermal cross-talk between adjacent PCM cells.Further reduction of heat loss can be obtained by providing anairgap-containing dielectric spacer laterally adjacent to the PCM cell.

In one aspect of the present application, a semiconductor structure isprovided. In one embodiment of the present application, thesemiconductor structure includes a phase change memory cell located on asurface of a semiconductor substrate. The phase change memory cell ofthe present application includes a phase change material sandwichedbetween a bottom electrode structure and a top electrode structure. Eachof the bottom electrode structure and the top electrode structure of thephase change memory cell includes a doped silicon germanium alloyelectrode positioned between a top diffusion barrier material and abottom diffusion barrier material.

In another aspect of the present application, a method of forming asemiconductor structure is provided. In one embodiment, the methodincludes providing a phase change memory cell on a surface of asemiconductor substrate. The phase change memory cell of the presentapplication includes a phase change material sandwiched between a bottomelectrode structure and a top electrode structure. Each of the bottomelectrode structure and the top electrode structure of the phase changememory cell includes a doped silicon germanium alloy electrodepositioned between a top diffusion barrier material and a bottomdiffusion barrier material.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a cross sectional view of an exemplary semiconductor structurein accordance with the present application and during an early stage offabrication, wherein the exemplary semiconductor structure includes aPCM material stack located on a surface of a semiconductor substrate.

FIG. 2 is a cross sectional view of the exemplary semiconductorstructure of FIG. 1 after patterning the PCM material stack.

FIG. 3 is a cross sectional view of the exemplary semiconductorstructure of FIG. 2 after forming a sacrificial spacer and an interleveldielectric (ILD) material layer laterally surrounding the patterned PCMmaterial stack.

FIG. 4 is a cross sectional view of the exemplary semiconductorstructure of FIG. 3 after removing the sacrificial spacer to provide agap between the ILD material layer and the patterned PCM material stack.

FIG. 5 is a cross sectional view of the exemplary semiconductorstructure of FIG. 4 after forming an airgap-containing dielectric spacerin the gap.

FIGS. 6A-6B are cross sectional views of other exemplary semiconductorstructures of the present application in which is no airgap-containingdielectric spacer is formed.

DETAILED DESCRIPTION

The present application will now be described in greater detail byreferring to the following discussion and drawings that accompany thepresent application. It is noted that the drawings of the presentapplication are provided for illustrative purposes only and, as such,the drawings are not drawn to scale. It is also noted that like andcorresponding elements are referred to by like reference numerals.

In the following description, numerous specific details are set forth,such as particular structures, components, materials, dimensions,processing steps and techniques, in order to provide an understanding ofthe various embodiments of the present application. However, it will beappreciated by one of ordinary skill in the art that the variousembodiments of the present application may be practiced without thesespecific details. In other instances, well-known structures orprocessing steps have not been described in detail in order to avoidobscuring the present application.

It will be understood that when an element as a layer, region orsubstrate is referred to as being “on” or “over” another element, it canbe directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “beneath” or “under” another element, it can bedirectly beneath or under the other element, or intervening elements maybe present. In contrast, when an element is referred to as being“directly beneath” or “directly under” another element, there are nointervening elements present.

Referring now to FIG. 1, there is illustrated an exemplary semiconductorstructure in accordance with the present application and during an earlystage of fabrication, wherein the exemplary semiconductor structureincludes a PCM material stack 100 located on a surface of asemiconductor substrate 10.

The semiconductor substrate 10 that can be employed in the presentapplication includes at least one semiconductor material that hassemiconducting properties. Examples of semiconductor materials that canbe used as the semiconductor substrate 10 include, for example, silicon(Si), a silicon germanium (SiGe) alloy, a silicon germanium carbide(SiGeC) alloy, germanium (Ge), III/V compound semiconductors or II/VIcompound semiconductors. In one embodiment, the semiconductor substrate10 is a bulk semiconductor substrate. The term “bulk semiconductorsubstrate” denotes a substrate that is composed entirely of one or moresemiconductor materials. In one example, the bulk semiconductorsubstrate is composed entirely of Si.

In some embodiments, the semiconductor substrate 10 is composed of asemiconductor-on-insulator substrate (SOI). A SOI substrate typicallyincludes a handle substrate, an insulator layer and a topmostsemiconductor material layer. In some embodiments, the handle substrateof the SOI may include a semiconductor material, as described above. Inother embodiments, the handle substrate may be omitted, or the handlesubstrate may be composed of a conductive material and/or an insulatormaterial. The insulator layer of the SOI substrate may include acrystalline or non-crystalline dielectric material. In one example, theinsulator layer of the SOI substrate may be composed of silicon dioxideand/or boron nitride. The topmost semiconductor layer of the SOIsubstrate is composed of a semiconductor material, as defined above.

Although not shown, the semiconductor substrate 10 may be processed toinclude one or more semiconductor devices such as, for example,transistors, capacitors, diodes, resistors, conductive wires, and thelike. The semiconductor substrate 10 may also include one or moreisolation structures such as, for example, a trench isolation structure,formed therein.

The PCM material stack 100 includes, from bottom to top, a firstdiffusion barrier layer 22L, a first doped silicon germanium alloy layer24L, a second diffusion barrier layer 26L, a phase change memory layer28L, a third diffusion barrier layer 30L, a second doped silicongermanium alloy layer 32L, and a fourth diffusion barrier layer 34L. Insome embodiments, a second electrically conductive metal or metal alloycontaining layer 36L is located on the PCM material stack 100, and afirst electrically conductive metal or metal alloy containing layer 12L,a fifth diffusion barrier layer 14L, a third doped silicon germaniumalloy layer 16L, a sixth diffusion barrier layer 18L, and aselector-containing layer 20L are located beneath the PCM material stack100. In some embodiments, any one of the second electrically conductivemetal or metal alloy containing layer 36L, the first electricallyconductive metal or metal alloy containing layer 12L, the third dopedsilicon germanium alloy layer, (and the associated fifth and sixthdiffusion barrier layers 14L, 18L), and the selector-containing layer20L can be omitted from the exemplary structure.

The first electrically conductive metal or metal alloy containing layer12L can be composed of any conductive metal or metal alloy. Examples ofconductive metals that can be used as the first electrically conductivemetal or metal alloy containing layer 12L include, but are not limitedto, copper (Cu), aluminum (Al), tungsten (W) or cobalt (Co). An exampleof a conductive metal alloy that may be used as the first electricallyconductive metal or metal alloy containing layer 12L includes acopper-aluminum alloy. The first electrically conductive metal or metalalloy containing layer 12L may include a single layered structurecomposed entirely of one conductive metal or metal alloy or amultilayered structure containing at least two different conductivematerials stacked one atop the other.

The first electrically conductive metal or metal alloy containing layer12L can be formed utilizing a deposition process such as, for example,chemical vapor deposition (CVD), plasma enhanced chemical vapordeposition (PECVD), atomic layer deposition (ALD), sputtering orplating. The first electrically conductive metal or metal alloycontaining layer 12L typically has a thickness from 10 nm to 200 nm;although other thicknesses for the first electrically conductive metalor metal alloy containing layer 12L are contemplated and can be used inthe present application.

In the present application, a diffusion barrier layer is formed aboveand below each doped silicon germanium alloy layer that is present inthe exemplary structure so as to prevent unwanted out-diffusion ofdopant from the doped silicon germanium alloy layer. The variousdiffusion barrier layers (14L, 18L, 22L, 26L, 30L and 34L) are composedof a diffusion barrier material than can prevent diffusion of dopantfrom the doped silicon germanium alloy layer into the other materiallayers of the exemplary structure. Examples of such diffusion barriermaterials that can be used as in providing the various diffusion barrierlayers (14L, 18L, 22L, 26L, 30L and 34L) include, but are not limitedto, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titaniumnitride (TiN), ruthenium (Ru), ruthenium nitride (RuN), a rutheniumtantalum (RuTa) alloy, RuTaN, or tungsten nitride (WN). In someembodiments, TiN or TaN is used as the diffusion barrier material foreach of the various diffusion barrier layers (14L, 18L, 22L, 26L, 30Land 34L).

The various diffusion barrier layers (14L, 18L, 22L, 26L, 30L and 34L)can be formed utilizing a deposition process such as, for example, CVD,PECVD, ALD, sputtering or plating. The various diffusion barrier layers(14L, 18L, 22L, 26L, 20L and 24L) can have a thickness from 10 nm to 25nm; however other thicknesses are contemplated and can be used as thethickness for each of the various diffusion barrier layers (14L, 18L,22L, 26L, 30L and 34L). The various diffusion barrier layers (14L, 18L,22L, 26L, 30L and 34L) may comprise a same or different diffusionbarrier material, and/or they may have a same or a different thickness.

The first, second and third doped silicon germanium alloy layers (16L,24L, 32L) are composed of a silicon germanium alloy that contains ap-type dopant or an n-type dopant. The term “p-type” refers to theaddition of impurities to an intrinsic semiconductor that createsdeficiencies of valence electrons. In a silicon-containing semiconductormaterial such as a silicon germanium alloy, examples of p-type dopants,i.e., impurities, include, but are not limited to, boron, aluminum,gallium and indium. “N-type” refers to the addition of impurities thatcontributes free electrons to an intrinsic semiconductor. In a siliconcontaining semiconductor material such as a silicon germanium alloy,examples of n-type dopants, i.e., impurities, include, but are notlimited to, antimony, arsenic and phosphorous. In one example, a borondoped silicon germanium alloy is used as the material for the first,second and third doped silicon germanium alloy layers (16L, 24L, 32L).The concentration of dopant (p-type or n-type) within the first, secondand third doped silicon germanium alloy layers (16L, 24L, 32L) istypically from 1×10¹⁹ atoms/cm³ to 2×10²¹ atoms/cm³.

The silicon germanium alloy that provides the first, second and thirddoped silicon germanium alloy layers (16L, 24L, 32L) may have agermanium content that is from 10 atomic percent germanium to 70 atomicpercent. Other germanium contents for the silicon germanium alloy thatprovides the first, second and third doped silicon germanium alloylayers (16L, 24L, 32L) are possible and are thus not excluded from beingused in the present application. The various silicon germanium alloylayers may have a same or different type of dopant, and/or a same ordifferent dopant concentration, and/or a same or different germaniumcontent, and/or a same or different thickness.

The first, second and third doped silicon germanium alloy layers (16L,24L, 32L) can be formed utilizing a deposition process such as, forexample CVD or PECVD. The deposition process can include the use of asilicon precursor gas and a germanium containing gas, or a combinedsilicon-germanium precursor gas. In some embodiments, the dopant can beintroduced in-situ during the deposition process. In other embodiments,the dopant can be introduced after the deposition of an intrinsicsilicon germanium alloy layer utilizing plasma doping, gas phase doping,ion implantation or dopant diffusion from a sacrificial material thatcontains the dopant. In some embodiments, an anneal process such as, forexample, a laser anneal can be used to activate dopants in the silicongermanium alloy layer(s).

The first, second and third doped silicon germanium alloy layers (16L,24L, 32L) may have a thickness from 20 nm to 200 nm. Other thicknessesfor the first, second and third doped silicon germanium alloy layers(16L, 24L, 32L) are contemplated and can be used as the thickness of thefirst, second and third doped silicon germanium alloy layers (16L, 24L,32L).

The phase change memory layer 28L includes a single phase changematerial or a vertical stack of at least two different phase changematerials. The phase change material(s) that provides the phase changememory layer 28L may be composed of a chalcogenide. Chalcogenides arecomprised of an element from Group 16 (i.e., a chalcogen) of thePeriodic Table of Elements and a more electropositive element. Examplesof chalcogens that can be used to provide the phase change materiallayer 28L include, but are not limited to, a GeSbTe alloy (GST), a SbTealloy, or an InSe alloy. Other materials can also be used as the firstphase change material so long as the other material can retain separateamorphous and crystalline states.

The phase change memory layer 28L can be formed by a deposition processsuch as, for example, CVD, PECVD or ALD. In some embodiments, the phasechange memory layer 28L can have a thickness from 20 nm to 250 nm. Otherthicknesses can also be employed as the thickness of the phase changememory layer 28L.

In some embodiments, and as is illustrated in FIG. 1, aselector-containing layer 20 can be present. When present, theselector-containing layer 20L includes at least one of a diode, athreshold switching device, etc. The selector-containing layer 20L canbe formed utilizing any suitable process that is well known to thoseskilled in the art. In some embodiments, transistors (e.g., bipolarjunction transistor (BJT) or metal-oxide-semiconductor field effecttransistor (MOSFET)) pre-built in the substrate 10 can be used as theselector in lieu of the selector-containing layer 20L.

The second electrically conductive metal or metal alloy containing layer36L can be composed of any conductive metal or metal alloy. Examples ofconductive metals that can be used as the second electrically conductivemetal or metal alloy containing layer 36L include, but are not limitedto, copper (Cu), aluminum (Al), tungsten (W) or cobalt (Co). An exampleof a conductive metal alloy that may be used as the second electricallyconductive metal or metal alloy containing layer 36L includes acopper-aluminum alloy. The second electrically conductive metal or metalalloy containing layer 36L may include a single layered structurecomposed entirely of one conductive metal or metal alloy or amultilayered structure containing at least two different conductivematerials stacked one atop the other.

The second electrically conductive metal or metal alloy containing layer36L can be formed utilizing a deposition process such as, for example,CVD, PECVD, ALD, sputtering or plating. The second electricallyconductive metal or metal alloy containing layer 36L typically has athickness from 10 nm to 200 nm; although other thicknesses for thesecond electrically conductive metal or metal alloy containing layer 36Lare contemplated and can be used in the present application.

Referring now to FIG. 2, there is illustrated the exemplarysemiconductor structure of FIG. 1 after patterning the PCM materialstack 100. In some embodiments, and when present, the secondelectrically conductive metal or metal alloy containing layer 36L thatis located on the PCM material stack 100, and the first electricallyconductive metal or metal alloy containing layer 12L, the fifthdiffusion barrier layer 14L, the third doped silicon germanium alloylayer 16L, the sixth diffusion barrier layer 18L, and theselector-containing layer 20L that are located beneath the PCM materialstack 100 are also patterned during this step of the presentapplication. Although the present application describes and illustratesthe formation of a single patterned PCM material stack, the presentapplication contemplates embodiments in which a plurality of spacedapart patterned PCM material stacks are formed.

The patterning can be performed by lithography and etching. Otherpatterning processes may also be used to pattern the PCM material stack100 and when present, the second electrically conductive metal or metalalloy containing layer 36L that is located on the PCM material stack100, and the first electrically conductive metal or metal alloycontaining layer 12L, the fifth diffusion barrier layer 14L, the thirddoped silicon germanium alloy layer 16L, the sixth diffusion barrierlayer 18L, and the selector-containing layer 20L that are locatedbeneath the PCM material stack 100.

The remaining PCM material stack 100 after patterning may be referred toas a patterned PCM material stack (or PCM cell) 102. The PCM cell 102includes a remaining portion of the first diffusion barrier layer 22L(hereinafter referred to a first diffusion barrier material 22), aremaining portion of the first doped silicon germanium alloy layer 24L(hereinafter referred to as a first doped silicon germanium alloyelectrode 24), a remaining portion of the second diffusion barrier layer26L (hereinafter referred to as a second diffusion barrier material 26),a remaining portion of the phase change memory layer 28L (hereinafterreferred to as a phase change memory structure 28), a remaining portionof the third diffusion barrier layer 30L (hereinafter referred to athird diffusion barrier material 30), a remaining portion of the seconddoped silicon germanium alloy layer 32L (hereinafter referred to as asecond doped silicon germanium alloy electrode 32), a remaining portionof the fourth diffusion barrier layer 34L (hereinafter referred to as afourth diffusion barrier material 34). Collectively, the first diffusionbarrier material 22, the first doped silicon germanium alloy electrode24, and the second diffusion barrier material 26 provide a bottomelectrode structure of the PCM cell 102, and collectively the thirddiffusion barrier material 30, the second doped silicon germanium alloyelectrode 32, and the fourth diffusion barrier material 34 provide a topelectrode structure of the PCM cell 102. In some embodiments, the PCMcell 102 when viewed from a top down view, is circular in shape. Othershapes, such as, for example, square, rectangular, etc., are possibleand can be employed in the present application.

If present, and after patterning, a remaining portion of secondelectrically conductive metal or metal alloy containing layer 36L(hereinafter second electrically conductive metal or metal alloystructure 36) is located above the PCM cell 102, and a remaining portionof the first electrically conductive metal or metal alloy containinglayer 12L (hereinafter first electrically conductive metal or metalalloy structure 12), a remaining portion of the fifth diffusion barrierlayer 14L (hereinafter fifth diffusion barrier material 14), a remainingportion of the third doped silicon germanium alloy layer 16L(hereinafter a third doped silicon germanium alloy electrode 16), aremaining portion of the sixth diffusion barrier layer 18L (hereinaftersixth diffusion barrier material 18), and a remaining portion of theselector-containing layer 20L (hereinafter selector 20) are locatedbeneath the PCM cell 102. Collectively, the fifth diffusion barriermaterial 14, the third doped silicon germanium alloy electrode 16, andthe sixth diffusion barrier 18 provide a heat loss prevention structurelocated between the selector 20 and the first electrically conductivemetal or metal alloy structure 12.

In some embodiments, the exemplary structure shown in FIG. 2 can beformed by first providing first electrically conductive metal or metalalloy structure 12 on a surface of the semiconductor substrate 10. Thefirst electrically conductive metal or metal alloy structure 12 can beformed first forming a first electrically conductive metal or metalalloy containing layer 12L and then patterning the first electricallyconductive metal or metal alloy containing layer 12L by lithography andetching. The other material layers within the exemplary structure canthen be formed, and thereafter those other material layers can bepatterned.

Referring now to FIG. 3, there is illustrated the exemplarysemiconductor structure of FIG. 2 after forming a sacrificial spacer 40and an interlevel dielectric (ILD) material layer 42 laterallysurrounding the patterned PCM material stack (i.e., PCM cell 102). As isshown in the illustrated embodiment, the sacrificial spacer 40 ispresent directly on the exposed sidewall of the PCM cell 102, and theILD material layer 42 is located on a sidewall of the sacrificial spacer40. In embodiments, in which second electrically conductive metal ormetal alloy structure 36 is located above the PCM cell 102, and firstelectrically conductive metal or metal alloy structure 12, fifthdiffusion barrier material 14, third doped silicon germanium alloyelectrode 16, sixth diffusion barrier material 18, and selector 20 arelocated beneath the PCM cell 102, the sacrificial spacer 40 is presentalong an exposed sidewall of those elements as well. Also, and as isshown in the illustrated embodiment, each of the sacrificial spacer 40and the ILD material layer 42 has a topmost surface that is coplanarwith a topmost surface of second electrically conductive metal or metalalloy structure 36. In embodiments, in which no second electricallyconductive metal or metal alloy structure 36 is present, each of thesacrificial spacer 40 and the ILD material layer 42 has a topmostsurface that is coplanar with a topmost surface of the PCM cell 102.

Sacrificial spacer 40 includes a spacer dielectric material that has adifferent composition than the dielectric material that provides the ILDmaterial layer 42. In one embodiment, the sacrificial spacer 40 mayinclude, for example, silicon dioxide, silicon nitride or siliconoxynitride. The sacrificial spacer 40 may be formed by first depositingthe spacer dielectric material, and thereafter patterning the depositedspacer dielectric material. The depositing of the spacer dielectricmaterial includes CVD, PECVC, PVD or ALD. The patterning of thedeposited spacer dielectric material can be performed utilizing a spaceretching process such as, for example, reactive ion etching. Thesacrificial spacer 40 may have a lateral thickness, i.e., width, from 5nm to 30 nm.

In one embodiment, the ILD material layer 42 can be composed silicondioxide, undoped silicate glass (USG), fluorosilicate glass (FSG),borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, achemical vapor deposition (CVD) low-k dielectric layer or anycombination thereof. The term “low-k” as used throughout the presentapplication denotes a dielectric material that has a dielectric constantof less than silicon dioxide. In another embodiment, a self-planarizingmaterial such as a spin-on glass (SOG) or a spin-on low-k dielectricmaterial such as SiLK™ can be used as ILD material layer 42. The use ofa self-planarizing dielectric material as the ILD material layer 42 mayavoid the need to perform a subsequent planarizing step. Although notshown, the ILD material layer 42 may comprise a multi-layered structurethat includes at least two different dielectric materials stacked oneatop the other such as, for example, silicon nitride and silicondioxide.

In one embodiment, the ILD material layer 42 can be formed utilizing adeposition process including, for example, CVD, PECVD, evaporation orspin-on coating. The thickness of the ILD material layer 42 may vary. Atypically thickness from the ILD material layer 42 is from 50 nm to 250nm. In some embodiments, particularly when non-self-planarizingdielectric materials are used as the ILD material layer 42, aplanarization process or an etch back process follows the deposition ofthe dielectric material that provides the ILD material layer 42.

In one embodiment, the ILD material layer 42 can be formed utilizing adeposition process including, for example, chemical vapor deposition(CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation orspin-on coating. In some embodiments, particularly whennon-self-planarizing dielectric materials are used as the ILD materiallayer 42, a planarization process or an etch back process follows thedeposition of the dielectric material that provides the ILD material.

Referring now to FIG. 4, there is illustrated the exemplarysemiconductor structure of FIG. 3 after removing the sacrificial spacer40 to provide a gap 44 between the ILD material layer 42 and PCM stack102 and, if present between the ILD material layer 42 and secondelectrically conductive metal or metal alloy structure 36 that islocated above the PCM cell 102, and first electrically conductive metalor metal alloy structure 12, fifth diffusion barrier material 14, thirddoped silicon germanium alloy electrode 16, sixth diffusion barriermaterial 18, and selector 20 that are located beneath the PCM cell 102.

The sacrificial spacer 40 can be removed utilizing an etching processthat is selective in removing the sacrificial spacer material thatprovides the sacrificial spacer 42. In one example, and when siliconnitride is employed as the sacrificial spacer material for thesacrificial spacer 40, hot phosphoric acid can be used to remove thesame from the structure. Gap 44 may, in some embodiments, have an aspectratio (width to height) of from 1:3 to 1:20. Other aspect ratios arepossible for gap 44.

Referring now to FIG. 5, there is shown exemplary semiconductorstructure of FIG. 4 after forming an airgap-containing dielectric spacerin the gap 44. The airgap-containing dielectric spacer comprises adielectric material 46 that has an airgap 48 present therein. Thedielectric material 46 that provides the airgap-containing dielectricspacer is composed of any dielectric spacer material such as, forexample, silicon nitride. The airgap-containing dielectric spacer can beformed utilizing a non-conformal deposition process such as, forexample, PECVD. A planarization process may follow the depositionprocess that provides the airgap-containing dielectric spacer. In someembodiments, the airgap can be formed by first conformally deposited athin dielectric liner (e.g., 2 nm silicon nitride deposited by ALD)followed by a non-conformal deposition of a dielectric (e.g., siliconnitride deposited by PECVD process) to pinch off the top of theremaining gap to form the airgap 48.

Referring to FIGS. 6A-6B, there are shown other exemplary semiconductorstructures of the present application in which is no airgap-containingdielectric spacer is formed. The exemplary semiconductor structure ofFIG. 6A includes only the ILD material layer 42 present directly on theexposed sidewall of the patterned PCM cell 102, and is present along anexposed sidewall of second electrically conductive metal or metal alloystructure 36 that is located above the PCM cell 102, and firstelectrically conductive metal or metal alloy structure 12, fifthdiffusion barrier material 14, third doped silicon germanium alloyelectrode 16, sixth diffusion barrier material 18, and selector 20 thatare located beneath the PCM cell 102. The exemplary semiconductorstructure of FIG. 6A can be formed utilizing the basic processing stepsdescribe above with the omission of forming the sacrificial spacer 40,removing the sacrificial spacer and forming the air-gap containingspacer.

The exemplary semiconductor structure of FIG. 6B includes include apermanent spacer 45 present directly on the exposed sidewall of thepatterned PCM cell 102, and is present along an exposed sidewall ofsecond electrically conductive metal or metal alloy structure 36 that islocated above the PCM cell 102, and first electrically conductive metalor metal alloy structure 12, fifth diffusion barrier material 14, thirddoped silicon germanium alloy electrode 16, sixth diffusion barriermaterial 18, and selector 20 that are located beneath the PCM cell 102.The exemplary semiconductor structure of FIG. 6B can be formed byutilizing the basic process steps described above with the exceptionthat the sacrificial spacer 42 is left within the structure to providethe permanent spacer 45 as shown in FIG. 6B.

Notably, FIGS. 5, 6A and 6B illustrate a semiconductor structure inaccordance with the present application that includes a phase changememory cell 102 located on a surface of a semiconductor substrate 10.The phase change memory cell 102 includes a phase change material 28sandwiched between a bottom electrode structure (22/24/26) and a topelectrode structure (30/32/34). Each of the bottom electrode structure(22/24/26) and the top electrode structure (30/32/34) of the phasechange memory cell 102 includes a doped silicon germanium alloyelectrode (24 or 32) positioned between top and bottom diffusion barriermaterials (22 and 26 or 30 and 34). Heat loss is mitigated in the phasechange memory cell 102 due to the presence of the doped silicongermanium electrodes (24 and 32). Further heat loss is avoided byproviding an airgap-containing spacer (46/48) along a sidewall of thephase change memory cell 102.

While the present application has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present application. It is therefore intended that the presentapplication not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

What is claimed is:
 1. A semiconductor structure comprising: a phasechange memory cell located on a surface of a semiconductor substrate,wherein the phase change memory cell comprises a phase change materialsandwiched between a bottom electrode structure and a top electrodestructure, wherein each of the bottom electrode structure and the topelectrode structure comprises a doped silicon germanium alloy electrodepositioned between a top diffusion barrier material and a bottomdiffusion barrier material, wherein the top and bottom diffusion barriermaterials are composed of a material that prevents diffusion of dopantsfrom the doped silicon germanium alloy electrode into the phase changematerial, and the material that prevents diffusion of the dopants isselected from the group consisting of tantalum (Ta), tantalum nitride(TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), rutheniumnitride (RuN), a RuTa alloy, RuTaN, and tungsten nitride (WN).
 2. Thesemiconductor structure of claim 1, wherein the doped silicon germaniumalloy comprises an n-type dopant or a p-type dopant.
 3. Thesemiconductor structure of claim 1, wherein the doped silicon germaniumalloy is composed of a boron doped silicon germanium alloy.
 4. Thesemiconductor structure of claim 1, further comprising a secondelectrically conductive metal or metal alloy structure located above thephase change memory cell.
 5. The semiconductor structure of claim 4,further comprising a first electrically conductive metal or metal alloystructure and a separator located beneath the phase change memory cell.6. The semiconductor structure of claim 5, further comprising a heatloss prevention structure located between the first electricallyconductive metal or metal alloy structure and the separator, wherein theheat loss prevention structure comprises another doped silicon germaniumalloy electrode located between upper and lower diffusion barriermaterials.
 7. The semiconductor structure of claim 1, further comprisingan airgap-containing dielectric spacer located along a sidewall of thephase change memory cell.
 8. The semiconductor structure of claim 7,further comprising an interlayer dielectric material layer laterallysurrounding the airgap-containing dielectric spacer.
 9. Thesemiconductor structure of claim 1, further comprising a permanentspacer located along a sidewall of the phase change memory cell, and aninterlayer dielectric material laterally surrounding the permanentspacer.
 10. The semiconductor structure of claim 1, further comprisingan interlayer dielectric material along a sidewall of the phase changememory cell.
 11. The semiconductor structure of claim 1, wherein thephase change memory cell is circular in shape.
 12. A method of forming asemiconductor structure, the method comprising: providing a phase changememory cell on a surface of a semiconductor substrate, wherein the phasechange memory cell comprises a phase change material sandwiched betweena bottom electrode structure and a top electrode structure, wherein eachof the bottom electrode structure and the top electrode structurecomprises a doped silicon germanium alloy electrode positioned between atop diffusion barrier material and a bottom diffusion barrier material,wherein the top and bottom diffusion barrier materials are composed of amaterial that prevents diffusion of dopants from the doped silicongermanium alloy electrode into the phase change material, and thematerial that prevents diffusion of the dopants is selected from thegroup consisting of tantalum (Ta), tantalum nitride (TaN), titanium(Ti), titanium nitride (TiN), ruthenium (Ru), ruthenium nitride (RuN), aRuTa alloy, RuTaN, and tungsten nitride (WN).
 13. The method of claim12, wherein the providing of the phase change memory cell includesforming a second electrically conductive metal or metal alloy structureabove the phase change memory cell.
 14. The method of claim 13, whereinthe providing of the phase change memory cell includes forming a firstelectrically conductive metal or metal alloy structure and a separatorbeneath the phase change memory cell, wherein a heat loss preventionstructure is positioned between the first electrically conductive metalor metal alloy structure and the separator, wherein the heat lossprevention structure comprises another doped silicon germanium alloyelectrode positioned between upper and lower diffusion barriermaterials.
 15. The method of claim 12, further comprising forming anairgap-containing spacer along a sidewall of the phase change memorycell.
 16. The method of claim 15, wherein the forming of theairgap-containing spacer comprises: forming a sacrificial spacer alongthe sidewall of the phase change memory cell; forming an interlayerdielectric material layer laterally surrounding the sacrificial spacer;removing the sacrificial spacer to provide a gap between the interlayerdielectric material layer and the phase change memory cell; anddepositing a dielectric material within the gap.
 17. The method of claim12, further comprising forming a permanent spacer located along asidewall of the phase change memory cell, and an interlayer dielectricmaterial surrounding the permanent spacer.
 18. The method of claim 12,further comprising forming an interlayer dielectric material along asidewall of the phase change memory cell.